Generally, the present invention relates to the formation of integrated circuits, and, more particularly, to the formation of metallization layers including silicide interconnect structures embedded into a dielectric material.
In an integrated circuit, a very large number of circuit elements, such as transistors, capacitors, resistors and the like, are formed in or on an appropriate substrate, usually in a substantially planar configuration. Due to the large number of circuit elements and the required complex layout of advanced integrated circuits, the electrical connections of the individual circuit elements are generally not established within the same level on which the circuit elements are manufactured. Typically, such electrical connections are formed in one or more additional “wiring” layers, also referred to as metallization layers. These metallization layers generally include metal-containing lines, providing the inner-level electrical connection, and a plurality of inter-level connections, also referred to as contacts or vias, filled with an appropriate highly conductive material. Contacts provide connections to devices such as transistors (e.g., connections to source, drain, or gate regions), while vias provide electrical connection between two neighboring stacked metallization layers. The metal-containing lines, contacts, and vias are commonly referred to as interconnect structures.
As the feature sizes of circuit elements in modern integrated circuits shrink, the number of circuit elements for a given chip area (i.e., packing density) increases, thereby requiring an increase in the number of electrical interconnections to provide the desired circuit functionality. Hence, the number of stacked metallization layers may increase and the dimensions of the individual lines and vias may be reduced as the number of circuit elements per chip area becomes larger. The fabrication of a plurality of metallization layers requires that issues relating to mechanical, thermal, and electrical reliability be addressed. Complex integrated circuits require conductive interconnects that can withstand moderately high current densities.
In some devices, materials such as tungsten (W) are used for contacts that interface with the transistors at the device level, also referred to as Metal1. However, as device dimensions decrease, the resistance and variability associated with tungsten also increases. Tungsten is typically deposited by means of chemical vapor deposition (CVD) technology, resulting in the possibility of an undesirable center seam and exaggerated electron-scattering-driven increases in resistivity as small dimensions. One potential replacement for tungsten is copper (Cu). Copper at the contact level provides significantly lower resistance, but raises issues with respect to barrier integrity and voiding. Copper has an affinity to react with silicon and can form copper silicide at low temperatures. Copper voiding in a contact structure may also occur due to the aggressive aspect ratios of the contacts.
Another challenge for fabricating interconnect structures is the resistance of the metal layer disposed on top of the contact. At one point, aluminum was used, but current devices typically employ copper formed using a damascene process. In a damascene process, a dielectric layer is formed over the underlying conductive feature. Openings are etched into the dielectric layer to expose the conductive feature, and the openings are filled with metal (e.g., with copper). Copper is a low resistance material, but it must be contained using barrier materials such as tantalum and tantalum nitride disposed between the copper and the surrounding dielectric material to prevent unwanted out-diffusion of copper into the dielectric, or else in-diffusion of moisture or oxygen, causing copper oxidation. The barrier thickness does not scale with the device dimensions, as a minimum thickness is required to establish the barrier. Thus, as the line width of the copper feature is reduced, the ratio of the cross-sectional area of the copper to the cross-sectional area of the line decreases, which rapidly increases the overall resistance.
As device dimensions continue to decrease, the width of the metal lines is approaching the mean free path of electrons in copper (i.e., 37 nm). Electrons in copper of line widths near this dimension will experience scattering from the sidewalls and surfaces, and with smaller grain sizes the grain boundary component will be higher. These scattering events also increase the resistance of the copper.
This section of this document is intended to introduce various aspects of art that may be related to various aspects of the disclosed subject matter described and/or claimed below. This section provides background information to facilitate a better understanding of the various aspects of the disclosed subject matter. It should be understood that the statements in this section of this document are to be read in this light, and not as admissions of prior art. The disclosed subject matter is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.